Simulation of fluorine implant effects in metal-gate FD-SOI and MuGFET

Lee, Chi-Woo;Lederer, Dimitri;Afzalian, Aryan;Yan, Ran;Colinge, Jean-Pierre
(2007) IEEK 2007 Summer Conference — Location: Korea (15.July.2007)

Files

C_13Simulationoffluorineimplanteffects.pdf
  • Restricted Access
  • Adobe PDF
  • 356.16 KB
Request a copy

Details

Authors
  • Lee, Chi-WooTyndall National Institute, University of Cork
    Author
  • Lederer, DimitriTyndall National Institute, University of Cork
    Author
  • Afzalian, AryanUCLouvain
    Author
  • Yan, RanTyndall National Institute, University of Cork
    Author
  • Colinge, Jean-PierreTyndall National Institute, University of Cork
    Author
Abstract
Fluorine (F) implantation creates negative charges at the Si/SiOa interface in FDSOI transistors[l]. This paper describes simulati n of the influence of F Implant on Threshold Voltage(Vth) for Metal Gate FDSOI and MuGFETs using FEMLAB. The origin of the large Vth shift observed in planar FDSOI due to is the creation of negative charge states in the BOX by the F implant. F implant is a suitable approach for planar FDSOI SoC integration with single work function (WF) metal gate, but NOT for MuGFETs.
Affiliations

Citations

  • APA
  • Chicago
  • FWB

Lee, C.-W., Lederer, D., Afzalian, A., Yan, R., & Colinge, J.-P. (2007). Simulation of fluorine implant effects in metal-gate FD-SOI and MuGFET. Proceedings of the IEEK 2007 Summer Conference, p. 2557-2558. https://hdl.handle.net/2078.5/252824