Performance of SOI devices transferred onto passivated HR SOI substrates using a layer transfer technique
(2006) 2006 IEEE International SOI Conference — Location: Niagara Falls, NY, USA (2.October.2006)
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- Abstract
- High resistivity (HR) silicon wafers are promising candidates for RF applications due, mainly, to their low cost, CMOS compatibility and substantial substrate loss reduction (Eggert et al., 1997). However, oxidized HR silicon (such as HR SOI material) is known to suffer from parasitic surface conduction (PSC) below the oxide (Gamble et al., 1999) which can reduce the effective resistivity ( rho /sub eff/) of the wafers by more than one order of magnitude (Lederer and Raskin, 2003). This issue can be overcome by introducing a trap-rich passivation layer between the oxide and the Si substrate, such as polysilicon (Gamble et al., 1999). In this paper we demonstrate for the first time that: (1) polySi substrate passivation can be efficiently realized on an industrial SOI technology using a post-process circuit transfer technique and that: (2) this technique preserves the performance of active devices.
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Lederer, D., Aspar, B., Laghae-Blanchard, C., & Raskin, J.-P. (2006). Performance of SOI devices transferred onto passivated HR SOI substrates using a layer transfer technique. 2006 IEEE International SOI Conference, p. 29-30. https://doi.org/10.1109/SOI.2006.284417