Noise Modeling and Performance in 0.15 µm Fully Depleted SOI MOSFET
(2004) SPIE Second International Symposium on Fluctuations and Noise — Location: Gran Canaria, Spain (25.May.2004)
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- Abstract
- This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.
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Citations
Pailloncy, G., Iniguez, B., Dambrine, G., Dehan, M., Raskin, J.-P., & et al. (2004). Noise Modeling and Performance in 0.15 µm Fully Depleted SOI MOSFET. Proceedings of SPIE vol. 5470, Noise in Devices and Circuits II, pp. 122-130. https://hdl.handle.net/2078.5/229432