A 7T-NDR Dual-Supply 28nm FD-SOI Ultra-Low Power SRAM with 0.23nW/kB Sleep Retention and 0.8pJ/32b Access at 64MHz with Forward Back Bias
(2023) IEEE Transactions on Circuits and Systems Part 1: Regular Papers — Vol. 70, n° 3, p. 1311-1323 (2023)
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- Authors
Kneip, Adrian 
- Abstract
- This work presents a 16kB ultra-low power (ULP)SRAM macro in 28nm FD-SOI with high energy efficiency in active mode and ultra-low leakage (ULL) in sleep mode, embedded in the SleepRider micro-controller unit (MCU) intended for IoT edge applications. The proposed SRAM integrates custom 7T ULL bitcells based on negative differential resistance (NDR) structures and a pMOS-only write port, achieving 2.1x lower area than previous NDR-based bitcells. A dual-supply strategy combined with negative-wordline write-assist concurrently provides worst-case data retention and correct write operations, up to the 64-MHz MCU target frequency. The SRAM macro periphery combines several low-power techniques to extract the full potential of the novel 7T bitcells, reaching an unprecedented speed-energy-leakage optimum with only 2.5% area overhead. Adaptive forward body biasing (FBB) further improves active mode performance while ensuring robustness against PVT variations. Measurement results showcase a minimum energy point of 0.78pJ per 32b access (assuming 50% read/write) at 0.5V and 64MHz. Moreover, leakage power drops from 296nW/kB at 0.5V in idle conditions to 0.23nW/kB in sleep at the 0.46V data retention voltage (DRV), yielding more than 1000x leakage reduction. As such, the proposed SRAM achieves an excellent trade-off between area, leakage and energy in the 10-to-100MHz frequency range.
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Citations
Kneip, A., & Bol, D. (2023). A 7T-NDR Dual-Supply 28nm FD-SOI Ultra-Low Power SRAM with 0.23nW/kB Sleep Retention and 0.8pJ/32b Access at 64MHz with Forward Back Bias. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 70(3), 1311-1323. https://doi.org/10.1109/TCSI.2022.3230984 (Original work published 2023)