SOI Self-Aligned Single-Electron Memory
(2001) MAR01 Meeting of the American Physical Society 2001 — Location: Seattle (USA) (12.June.2001)
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- Abstract
- This paper reports on the fabrication of a SOI nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key process involved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channel MOSFET with a nanocrystal floating gate embedded in the gate oxide. The length, width and height of the nanocrystal are 10nm, 10nm and 20nm, respectively. As long as the control gate voltage does nor exceed 2V, the device behaves like a thin and narrow P-channel MOSFET. When a voltage of 5 or +5 volts is applied to the control gate at room temperature, holes are injected into the floating gate or removed from it, respectively. This effect includes a persistent shift of the threshold voltage of the device, which acts as a miniature EEPROM.
- Affiliations
Citations
Bayot, V., Tang, X., Baie, X., Colinge, J.-P., & Van de Wiele, F. (2001). SOI Self-Aligned Single-Electron Memory. MAR01 Meeting of the American Physical Society 2001, Seattle (USA). https://hdl.handle.net/2078.5/231699